In this post we talk about two of the most commonly used constructs in SystemVerilog – the if statement and the case statement. We have seen in a previous post how use procedural blocks such as the always block to…
In this blog post we look at the use of SystemVerilog parameters and the generate statement to write code which can be reused across multiple FPGA designs. This includes examples of a parameterized module, a generate for block, generate if…
In this post, we discuss one of the most important constructs in SystemVerilog design – the always block. As we discussed in the post on continuous assignment in SystemVerilog, there are two main classes of digital circuit which we can…
In this post we talking about creating our own data types in SystemVerilog using the typedef, enum and struct keywords. In a previous post, we talked about the basic predefined data types in SystemVerilog. Whilst these are adequate for the…
In this post, we primarily talk about the concept of continuous assignment in SystemVerilog. We also look at how we can use this in conjunction with the SystemVerilog operators to model basic combinational logic circuits. However, continuous assignment is a…
In this post, we talk about the different types of dynamic arrays we can use in SystemVerilog, including normal dynamic arrays and their associated methods, queues and their associated methods and finally associative arrays. As we talked about in a…
This post is the first in a series which discusses how SystemVerilog is used in FPGA design. We begin by looking at the way we structure a SystemVerilog design using the module keyword. This includes a discussion of parameters, ports…