How to Write a Basic Testbench using VHDL In this post we look at how we use VHDL to write a basic testbench. We start by looking at the architecture of a VHDL test bench. We then look at some…
In this post we look at how we use Verilog to write a basic testbench. We start by looking at the architecture of a Verilog testbench. We then look at some key concepts such as modelling time in verilog and…
This post is the first in a series which introduces the concepts and use of verilog for FPGA design. We start with a discussion of the way Verilog designs are structured using the module keyword and how this relates to…